Introduction to Trace Length and Time Delay in PCBs

In high speed printed circuit board (PCB) design, the physical length of traces between components has a significant impact on signal integrity. As signal speeds increase, the time it takes for a signal to propagate down a trace becomes a critical factor. This propagation time is known as the time delay.

To ensure proper timing and prevent issues like skew, jitter, and reflections, PCB designers need to carefully control the length of traces. One way to do this is by calculating the required trace length based on the desired time delay.

Relationship Between Trace Length and Time Delay

The relationship between trace length and time delay can be expressed with this formula:

Trace Length = Time Delay × Propagation Velocity

Where:
– Trace Length is in inches
– Time Delay is in nanoseconds (ns)
– Propagation Velocity is in inches per nanosecond (in/ns)

Propagation velocity depends on the dielectric constant (Dk) of the PCB substrate material. A higher Dk results in slower propagation velocity. Some common propagation velocities for different PCB materials are shown in this table:

PCB Material	Dk	Propagation Velocity (in/ns)
FR-4	4.0 – 4.5	5.9
Polyimide	3.5	6.7
PTFE (Teflon)	2.1	9.8

So for example, if you need a time delay of 1 ns on an FR-4 PCB, the required trace length would be:

1 ns × 5.9 in/ns = 5.9 inches

Determining Required Time Delays

Timing Considerations

Before you can calculate trace lengths, you first need to determine what time delays are required in your design. This depends on several factors:

1. Setup and hold times: ICs specify minimum setup and hold times for signals relative to a clock. Trace delays must ensure signals arrive within these timing windows.

2. Clock frequencies: Higher clock speeds leave smaller timing margins, so tighter control of trace delays becomes critical.

3. Bus topologies: Parallel busses may require equal length traces to avoid skew, while serial busses may use trace delay to help signals line up with a clock.

4. Signal rise/fall times: Fast rise and fall times are more susceptible to reflections from impedance discontinuities caused by unmatched trace lengths.

Calculating Time Delays

There are a few different ways to determine what time delays are needed:

1. Timing analysis: A timing analyzer tool can model propagation delays and identify timing violations to be corrected.

2. Simulation: Simulating a design with estimated trace delays can reveal problem areas that need timing adjustments.

3. Calculations: For simple cases, required delays can be calculated by hand based on IC timing specs and system requirements. Some example calculations:

To meet a setup time:
– Trace Delay ≤ Clock Period – Source Clock-to-Output Time – Destination Setup Time

To meet a hold time:

• Trace Delay ≥ Destination Hold Time – Source Clock-to-Output Time

For equal length traces on a parallel bus:
– Trace Delays Matched Within ± Allowable Skew

Calculating Trace Lengths

Once required time delays are known, you can calculate the corresponding trace lengths needed. Here are the steps:

1. Determine the propagation velocity based on your PCB material. Refer to the table above or consult your PCB vendor for the exact value.

2. For each time delay, multiply it by the propagation velocity to get the trace length:

Trace Length = Time Delay × Propagation Velocity

1. If necessary, convert units. Time delay is typically specified in nanoseconds, propagation velocity in in/ns, and trace length in inches. 1 inch = 25.4 mm if you need metric units.

Some examples:

• For a 1.5 ns delay on FR-4:
  1.5 ns × 5.9 in/ns = 8.85 inches

• For a 500 ps delay on PTFE:
  0.5 ns × 9.8 in/ns = 4.9 inches

• For a ±50 ps skew tolerance on a 3 inch Polyimide trace:
  50 ps × 6.7 in/ns = ±0.335 inches
  Allowable trace lengths: 2.665 to 3.335 inches

Accounting for Vias and Terminations

Vias and termination components like resistors also contribute to the total delay of a trace. When calculating trace lengths, you need to factor these in.

For vias, you can estimate the delay using this formula:

Via Delay = Via Length / (3 × Propagation Velocity)

Where via length is the thickness of the PCB. The factor of 3 accounts for the slower propagation velocity through the via barrel.

For example, a 0.062″ thick FR-4 PCB with vias would add this much delay:

0.062″ / (3 × 5.9 in/ns) = 3.5 ps per via

So if a trace has 2 vias, you would need to subtract 7 ps from your target delay to account for them.

Termination components like resistors also add a small propagation delay, typically just a few picoseconds. Consult vendor datasheets for specifications and include them in your length calculations if needed.

Implementing Calculated Trace Lengths

Routing Guidelines

Once you’ve calculated the required trace lengths, you need to implement them in your PCB layout. Here are some guidelines to follow:

1. Serpentine vs Delay Lines: If a trace needs to be lengthened, you can either route it in a serpentine pattern or use a dedicated delay line component. Serpentines are cheaper but take up more space and can cause impedance discontinuities. Delay lines are compact and well-controlled but add cost.

2. Symmetry: Differential pairs and other parallel traces should be routed symmetrically to maintain equal delays. Mirror the path of each trace to avoid skew.

3. Impedance Control: Maintain consistent trace width and spacing to avoid impedance mismatches that could cause reflections. Consult your PCB vendor for recommended geometries.

4. Minimize Vias: While via delays can be accounted for, it’s best to minimize the number of vias to keep delays predictable. Vias can also cause impedance and EMI issues at high frequencies.

5. Placement: To make trace delays more manageable, place ICs as close together as possible. This minimizes the amount of lengthening or shortening required.

6. Verification: After laying out traces, use a PCB Calculator tool to verify the actual delays match your calculations. Make adjustments as needed.

By carefully planning and implementing trace delays, you can ensure reliable high-speed communication in your PCB designs.

Adjusting for Manufacturing Variations

PCB manufacturing is not a perfect process, so you need to account for variations in your trace delays. Etching tolerances, substrate inconsistencies, and other factors can cause actual delays to deviate from calculated values.

To mitigate this, you can:

1. Overdesign: Use conservative delay targets that leave margin for manufacturing variations. For example, if you need a 1 ns delay, design for 0.95 ns to allow for ±50 ps of variation.

2. Specify Tolerances: Work with your PCB manufacturer to specify acceptable tolerances for trace delays. This may involve specifying tighter etching tolerances or using higher grade substrates.

3. Post-Manufacturing Testing: Perform tests on fabricated boards to measure actual trace delays. Compare against specifications and rework or scrap boards that are out of tolerance.

By allowing for manufacturing variations, you can ensure your carefully calculated delays are realized in the final product.

Conclusion

Controlling trace delays is a critical aspect of high-speed PCB design. By understanding the relationship between trace length and propagation delay, and using the techniques described here to calculate and implement precise trace lengths, you can ensure your designs will meet timing requirements and perform reliably. While it may seem daunting at first, with practice and attention to detail, you can master the art of trace delay management.

FAQ

What is the main reason trace length affects signal timing in high speed PCBs?

Trace length determines the propagation time, or time delay, of signals traveling between components. If not properly accounted for, these delays can cause timing violations and corrupt communications.

How do you calculate the right trace length for a given time delay?

Trace length is the product of the required time delay and the propagation velocity of the PCB material. Propagation velocity depends on the dielectric constant (Dk). You can look up standard propagation velocities or consult your PCB vendor for specific values.

What factors influence the choice of propagation velocity to use?

The main factor is the Dk of the PCB substrate material. Higher Dk materials like FR-4 have slower propagation velocities. Lower Dk materials like PTFE have faster velocities. The thickness of the dielectric layer can also have a minor effect.

How do vias affect trace delay calculations?

Vias add a small amount of delay due to the slower propagation velocity through the via barrel. The delay of each via can be estimated as the PCB thickness divided by 3 times the propagation velocity. This delay should be subtracted from the target trace delay.

What are some key routing guidelines to ensure trace delays match calculations?

1. Use serpentine routing or delay lines to lengthen traces as needed.
2. Route differential pairs and parallel busses symmetrically.
3. Maintain consistent trace impedance.
4. Minimize the number of vias.
5. Place components to minimize required trace lengths.
6. Verify actual delays after routing and make adjustments as needed.

By understanding and applying these concepts, PCB designers can tame signal timing and master the black art of high-speed design. With practice, you too can learn to wrangle wild delay lines and corral unruly clock domains. Go forth and conquer the high-speed frontier!