Differential trace impedance without reference plane

What is Differential Trace Impedance?

Differential trace impedance refers to the Characteristic Impedance of a differential pair of traces on a printed circuit board (PCB). A differential pair consists of two conductors that carry equal and opposite signals. The impedance of the pair is determined by the geometry and spacing of the traces as well as the properties of the dielectric material surrounding them.

Differential signaling is commonly used for high-speed digital interfaces like USB, PCIe, HDMI, Ethernet, and more. It offers advantages over single-ended signaling such as:

Improved noise immunity
Reduced electromagnetic interference (EMI)
Ability to drive signals over longer distances

To achieve these benefits, it’s important to carefully control the differential impedance of the traces. Mismatched impedance can lead to signal reflections, increased EMI, and degraded signal integrity.

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Calculating Differential Impedance

The differential impedance of a pair of traces depends on several factors:

Trace width (w)
Trace thickness (t)
Spacing between traces (s)
Height above reference plane (h)
Dielectric constant of material (εr)

There are various formulas and online calculators available to determine the differential impedance based on these parameters. One common approximation is:

Zdiff ≈ 2 × 87 / √εr × ln(1.9 × (2h + s) / (0.8w + t))

Where:
– Zdiff = differential impedance in ohms
– εr = dielectric constant of material
– h = height above reference plane in mils
– s = spacing between traces in mils
– w = trace width in mils
– t = trace thickness in mils

For example, consider a differential pair with the following properties:

Parameter	Value
Trace width (w)	5 mils
Trace thickness (t)	1.4 mils
Spacing between traces (s)	5 mils
Height above reference plane (h)	5 mils
Dielectric constant (εr)	4.5

Plugging these values into the equation above yields:

Zdiff ≈ 2 × 87 / √4.5 × ln(1.9 × (2×5 + 5) / (0.8×5 + 1.4))
≈ 2 × 87 / 2.12 × ln(15 / 5.4)
≈ 82 × 1.022
≈ 84 ohms

So this particular geometry would have a differential impedance of approximately 84 ohms. Common target impedances are 90 ohms for USB and 100 ohms for Ethernet and PCIe.

Designing for Target Impedance

To hit a specific target impedance, PCB designers can adjust the trace geometry and spacing. Typically the dielectric material and thickness are constrained by other factors, so the main variables are:

Trace width
Spacing between traces

In general, increasing the trace width will decrease the impedance, while increasing the spacing will increase it. Online calculators and field solver tools help designers converge on the right values.

Many PCB design tools have built-in features to calculate and tune differential impedance. The software models the trace cross-section and computes the impedance based on the Layer Stack-Up and material properties. More advanced field solvers use numerical methods like finite element analysis for greater accuracy.

Impact of the Reference Plane

The discussion so far has assumed the presence of an uninterrupted reference plane beneath the differential pair. This is typically a ground plane or power plane on an adjacent layer.

The reference plane serves several important functions:
– Provides a controlled return path for the differential currents
– Minimizes loop area and reduces inductance
– Shields the traces from external noise coupling
– Confines the electromagnetic fields to enable consistent impedance

However, in some cases it may not be possible or practical to provide a solid reference plane. Reasons could include:

Limited board space or layer count
Cut-outs or apertures required for components, mounting holes, etc.
Traces crossing splits in reference plane (e.g. different voltage areas)

Without a continuous reference plane, the impedance of the differential pair becomes more difficult to predict and control. The fields are no longer confined between the traces and the plane. Energy can couple into other structures or radiate as EMI.

Mitigation Strategies

PCB designers can use various techniques to mitigate the impact of reference plane disruptions on differential pairs:

Stitching Capacitors

One method is to “stitch” the two sides of a reference plane split back together using capacitors. The caps provide a low-impedance path for high-frequency noise currents. Typical values range from 100 pF to 100 nF depending on the frequency.

The capacitors should be placed close to the differential pair to minimize the discontinuity. Multiple caps can be used to reduce the effective inductance.

Differential Cutout

If a cutout in the reference plane is unavoidable, sometimes a “differential cutout” can be used. This involves cutting a similar slot beneath the other trace of the pair. The idea is to maintain symmetry between the two sides.

Ideally the differential cutout should match the original cutout in size, shape, and position relative to the trace. This technique works best for relatively small apertures.

Waveguides

For larger gaps in the reference plane, sometimes a waveguide structure can be used to contain the fields of the differential pair. The waveguide can take the form of a channel or tunnel in the PCB Stackup.

Conductive vias are used to stitch the upper and lower ground planes together, forming the sides of the waveguide. The dimensions of the waveguide must be carefully designed to control the impedance and cut-off frequency.

Suspension

In some cases it may be possible to simply route the differential pair over the reference plane gap without any special structures. This is called “suspending” the traces.

The success of this approach depends on the size of the gap and the operating frequency. At lower frequencies the impedance discontinuity may be tolerable. Simulation tools can predict the magnitude of any reflections.

Simulation and Measurement

Analyzing differential pairs without a reference plane is challenging due to the 3D nature of the fields. Simple 2D cross-section models are no longer sufficient.

Full-wave 3D electromagnetic simulation tools like Ansys HFSS, Keysight EMPro, or CST Studio can be used to model more complex structures. These tools solve Maxwell’s equations to predict the impedance, insertion loss, and other properties of the differential pair.

Simulation is valuable for comparing design options and optimizing the geometry. However, simulation models are never perfect and must be correlated with measurements on real hardware.

One common measurement technique is time domain reflectometry (TDR). A fast rise time pulse is injected into the differential pair while monitoring the reflected energy. Discontinuities appear as “bumps” in the reflectance waveform. The magnitude indicates the severity of the impedance mismatch.

Another method is to measure the insertion loss (s21) of the differential pair using a vector network analyzer (VNA). This shows the frequency dependence of the loss, which is impacted by impedance discontinuities. Excess insertion loss can point to trouble spots that may need redesign.

Conclusion

Maintaining consistent differential impedance is critical for high-speed PCB designs. While a solid reference plane makes this easier, it’s not always feasible. Disruptions to the reference plane can impact the impedance and cause signal integrity issues.

Careful design techniques such as stitching capacitors, differential cutouts, waveguides, or suspension can mitigate the impact. But there’s no one-size-fits-all solution. Simulation and measurement are key to validating the impedance and identifying any issues.

As data rates continue to rise, differential signaling and Impedance Control will become even more important. PCB designers must understand the principles and tradeoffs involved in breaking the reference plane. With the right tools and techniques, it’s possible to maintain good signal integrity despite these challenges.

Frequently Asked Questions (FAQ)

What is the typical impedance for differential pairs?

Common target impedances are:
– USB: 90 ohms
– PCIe: 100 ohms
– Ethernet: 100 ohms
– HDMI: 100 ohms

How does trace geometry affect differential impedance?

In general:
– Increasing the trace width decreases the impedance
– Increasing the spacing between traces increases the impedance
– Increasing the height above the reference plane decreases the impedance

What is the purpose of stitching capacitors?

Stitching capacitors provide a low-impedance path to reconnect a split reference plane at high frequencies. This helps contain the fields of the differential pair. Typical values range from 100 pF to 100 nF.

When is it okay to suspend differential pairs over a gap?

Suspending the traces may be feasible if:
– The gap is relatively small (less than ~1/10 wavelength)
– The operating frequency is low enough that reflections are tolerable
– Simulation shows no major impact on impedance or insertion loss

What tools are used to simulate differential pairs?

3D full-wave electromagnetic solvers like Ansys HFSS, Keysight EMPro, or CST Studio are commonly used. These tools can model complex structures and predict impedance, insertion loss, and other properties. Many PCB design tools also have built-in 2D field solvers for simple geometries.

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