DDR2 800 for PCB signal integrity design and DDR

Key Characteristics of DDR2 800

DDR2 800 SDRAM has the following key characteristics:

Operates at a clock frequency of 400 MHz with data transfers on both edges of the clock signal, providing an effective data rate of 800 MT/s (mega transfers per second)
Uses SSTL_18 (Stub Series Terminated Logic for 1.8V) for data, command, and address signaling
Has a prefetch buffer size of 4n (vs 2n for DDR)
Has 240 pins per DIMM module (vs 184 pins for DDR)
Uses a VDDQ voltage of 1.8V ±0.1V (vs 2.5V for DDR)

A comparison of DDR2 800 to other DDR2 speed grades is shown in the table below:

Parameter	DDR2 400	DDR2 533	DDR2 667	DDR2 800
Clock Rate (MHz)	200	266	333	400
Data Rate (MT/s)	400	533	667	800
SSTL Voltage	1.8V	1.8V	1.8V	1.8V
Prefetch Size	4n	4n	4n	4n
Pins per DIMM	240	240	240	240

Request Ceramic PCB Manufacturing & Assembly Quote Now

Signal Integrity Challenges with DDR2

As clock frequencies increase, the signal integrity challenges of routing memory signals on a PCB become greater. Some of the key challenges include:

Reflections and Impedance Discontinuities

Impedance discontinuities caused by uncontrolLED PCB trace impedances, improper terminations, vias, and connectors can result in reflections that corrupt data signals. At high frequencies, even small discontinuities can cause significant reflections.

Crosstalk

As edge rates become faster and traces are routed closer together to make routing easier, the coupling between signals increases. This crosstalk can cause jitter and reduce noise margins, leading to data corruption.

Attenuation and Intersymbol Interference

As frequencies increase, the attenuation experienced by signals also increases. If the high-frequency components of a signal are attenuated too much, the signal can become distorted and the receiver may not be able to recover the data. This is known as intersymbol interference (ISI).

Power Integrity

At higher frequencies, the transient current demands of memory devices become greater. This can cause power supply noise that degrades signal integrity. Careful PDN (power distribution network) design is critical.

Best Practices for DDR2 PCB Design

To overcome the signal integrity challenges associated with DDR2 and create a reliable design, the following best practices should be followed:

Controlled Impedance Routing

DDR2 signals should be routed on controlled impedance transmission lines. The PCB Stackup should be designed to provide the target impedances (typically 50Ω single-ended and 100Ω differential). Trace widths and spacing to reference planes must be tightly controlled.

Length Matching

To minimize skew between signals, trace lengths should be tightly matched. For read/write data strobes (DQS) and data lines (DQ), the maximum mismatch is ±20 ps. For address/command lines the maximum skew is ±125 ps. Serpentine routing techniques can be used to add length to shorter traces.

Terminations

Parallel termination resistors should be used at the DRAM end of the bus to minimize reflections. The resistor value should be chosen to match the trace impedance (typically 20-30Ω for SSTL_18). Fly-by termination should be used, rather than T-branches, to avoid impedance discontinuities.

Via Control

The number of vias in DDR2 signals should be minimized as much as possible, as vias represent impedance discontinuities and can cause reflections. Any unavoidable vias should be placed near the driver end of the signal. Back-drilling can be used to remove the unused portion of the via stub.

Power Distribution

Decoupling capacitors should be placed close to DRAM power pins to minimize inductance and supply clean power. Typically a combination of bulk (10-100 μF) and ceramic (0.1 μF and 0.01 μF) capacitors are used in parallel. The PCB stackup should include power and ground planes for low impedance.

Example DDR2 Routing Topology

The diagram below shows an example topology for routing DDR2 signals on a PCB:

        [CPU]
         |
   [Termination]
         |
   .-----'-----.  
   |           |
  [DRAM]     [DRAM]

In this topology, DDR2 signals are routed in a fly-by fashion from the CPU to each DRAM in series. The termination resistors are placed near the last DRAM. This arrangement provides clean signaling but does require length-matching between the two DRAM branches.

DDR2 Layout Checklist

When laying out a DDR2 interface on a PCB, use the following checklist to ensure all key requirements have been met:

[ ] Controlled impedance stackup designed and specified to fabricator
[ ] All DDR2 signals routed on controlled impedance traces
[ ] DQ/DQS signals length-matched to ±20 ps
[ ] Address/command signals length-matched to ±125 ps
[ ] Parallel termination resistors used at end of bus
[ ] Fly-by topology used (no T-branches)
[ ] Vias minimized and placed near driver
[ ] Back-drilling used on vias if possible
[ ] Decoupling capacitors placed near DRAM power pins
[ ] Power and ground planes included in stackup

Simulation and Measurement

While following best layout practices goes a long way towards ensuring DDR2 signal integrity, it is highly recommended to perform pre- and post-layout simulation to verify the design. A SPICE circuit simulator with an S-parameter model of the PCB interconnects can be used to simulate eye diagrams and analyze timing.

Post-fabrication, measurements should also be performed on the Prototype PCB to correlate simulation results and verify that the DDR2 interface is working as expected. A high-bandwidth oscilloscope with an active probe can be used to capture eye diagrams.

Conclusion

Designing a PCB for a DDR2 interface presents many signal integrity challenges due to the high frequencies involved. However, by understanding these challenges and following best practices for PCB design – including controlled impedances, length matching, proper termination, and power distribution – a reliable DDR2 implementation can be achieved. Simulation and measurement are also key to validating the design and ensuring robust performance.

FAQ

What is the difference between DDR2 and DDR3?

The main differences between DDR2 and DDR3 are:
– DDR3 has higher data rates (up to 2133 MT/s)
– DDR3 uses lower voltages (1.5V or 1.35V)
– DDR3 has higher latencies (CAS latency of 9-11 vs 3-6 for DDR2)
– DDR3 uses a fly-by command/address bus topology

Can DDR2 and DDR3 be used interchangeably?

No, DDR2 and DDR3 modules have different pin assignments and signaling voltages so they are not compatible. A system must be designed for either DDR2 or DDR3.

What is the purpose of a termination resistor?

A termination resistor is used at the end of a transmission line to absorb energy and prevent reflections. Without termination, reflections from the end of the line can interfere with the original signal and cause data corruption.

Why is length matching important for DDR2 signals?

Length matching is important to minimize skew between related signals, such as data and strobe lines. If the signals arrive at the receiver at different times, it becomes difficult to capture the data reliably. The tighter length matching requirements for data lines is due to the need to capture the data synchronously with the strobe.

What is a stackup and why is it important?

A PCB stackup refers to the arrangement of copper layers and dielectrIC Substrates that make up the circuit board. The stackup determines the impedances of the traces on the board. For DDR2, careful stackup design is critical to produce the target impedances needed for the memory signals. The stackup also provides power and ground planes for the PDN.

Ceramic PCB